The following acronyms will be used in the description of both the prior art and the invention:
PI: Proportional and Integrating controller
PID: Proportional, Integrating and Derivating controller
SDH: Synchronous Digital Hierarchy, a digital data transmission technology
Transmission of digital data between two different data network elements is performed so that a certain amount of bit data is sent to the transmission channel in the sending network element in consecutive cycles of the timing signal. The number of bits sent during the cycle, and the frequency of the timing signal determine the data transfer rate. For example, when 8 bits/cycle are transmitted at the frequency of 1 MHz of the timing signal, the data transfer rate is 8 Mbit/s.
Typically, in a digital data transmission network there are consecutive subareas in the propagation direction of the transmission, in which the nominal data transfer rates are different, or in which the nominal data transfer rates are the same but the phases of their timing signals shift in relation to each other. These subareas of the data transmission network are thus asynchronous in relation to each other. The fact that the phases of the timing signals can shift in relation to each other means that the instantaneous data transfer rates of different subareas can differ from each other, even if the average data transfer rates were equal. When moving across the border between two such subareas, it is necessary to perform speed adjustment, which takes into account the different data transfer rates. If the average data transfer rates differ from each other, speed adjustment is performed by increasing or decreasing the number of bits transmitted in a certain time window. Increasing is carried out by using additional bits, which can be mere stuffing bits, or they can, for example, represent the heading, control, separator and other such information of frame and/or packet structures related to the transmission protocol. Decreasing is carried out by removing said additional bits, which is done when moving from a faster subarea to a slower one. If the average data transfer rates are equal, speed adjustment can be carried out by buffering.
FIG. 1 shows an exemplary data communication network, which is used for describing the prior art. The data communication network shown in FIG. 1 has three subareas A 101, A 102 and A 103. The nominal data transfer rates of subareas A 102 and A103 are the same, but the system has no timing signal common to subareas A101 and A102. In order to make the situation sensible, the temporal average of the data transfer rate of subarea A 102 must be at least equal to the temporal average of the data transfer rate of subarea A101.
In the situation being examined as an example, the operation is as follows:                The digital data stream D101 produced by the user K101 of the data transmission service arrives at the network element VE101 located at the border of subareas A101 and A102 as synchronized by the timing signal CLK101.        Speed adjustment SA101 is performed in the network element VE101, resulting in a data stream D102.        A data stream D102 is received in the network element VE102 located at the border of subareas A102 and A103, and speed adjustment SA102 is performed on it, resulting in the original data stream D101.        A timing signal CLK102 is generated in the network element VE102 on the basis of the speed of arrival of the portion of the data stream D102 being received, which represents the data stream D101. In other words, the timing signal CLK102 is regenerated. The data stream D101 is sent to another user K102 of the data communication network as synchronized by the timing signal CLK102.        The digital data stream U101 produced by the user K102 arrives at the network element VE102 as synchronized by the timing signal CLK102.        Speed adjustment SA 103 is performed in the network element VE102, resulting in a data stream U102.        The data stream U102 is received in the network element VE101, speed adjustment SA104 is performed on it, and the result is the original data stream U101. The data stream U101 is sent to the user K101 of the data communication network as synchronized by the timing signal CLK101.        
The objective is thus to generate the timing signal CLK102 in the network element VE102 so that the momentary frequency of the timing signal is as close to the momentary frequency of the timing signal CLK101 as possible. If the timing signal CLK102 could be formed such that its momentary frequency were continuously the same as the momentary frequency of the timing signal CLK101, the users K101 and K102 of the data communication network would not be able to notice that there are subareas in the network in which the average and/or momentary data transfer rates differ from each other. With regard to the quality of the data transmission service, it is essential that the momentary frequency of the regenerated timing signal CLK102 does not differ too much from the momentary frequency of the timing signal CLK101. For this reason, international standardization organizations, such as ITU (International Telecommunication Union), have set limits on frequency deviations of different frequencies.
In the mode of operation described above, the network element VE101 functions as the master with regard to mutual synchronization of subareas A 101 and A 103 of the network, and the network element VE102 functions as the slave. Duplex data transmission functions in a master/slave loop timing mode, in which the timing signal CLK102 regenerated in the slave VE102 is used in the slave for synchronizing the data transmission of both transmission directions.
The method by which the timing signal is generated for receiving the data stream D102 in the network element VE102 is not significant with regard to the present invention. Said timing signal can be generated e.g. by means of the data stream D102 being received, using conventional synchronization methods, or a reference clock signal can be spread in the subarea A102 of the network, like in SDH (Synchronous Digital Hierarchy) networks. The same applies to the reception of the data stream U102 in the network element VE101.
The regeneration of the timing signal CLK102 is made more difficult by the fact that the data transmission delay between the network elements VE101 and VE102 is a variable quantity. Packet-switched data networks, in particular, tend to cause a strong variation in the transmission delay, but the conventional time slot switched data transmission networks also cause variation in the delay. Another phenomenon, which makes it more difficult to regenerate the timing signal, is the loss of data being transferred at times as a result of congestion of the network or other interference.
A prior art method for generating a timing signal in a slave in the master-slave timing modes of the type described above is presented in FIG. 2. The speed adjustment block SA102 includes means P201, by which the bits that are unnecessary and would actually be harmful in the resulting data stream D101, are removed from the arriving data stream D102. The removal of the bits is not required if the data streams D101 and D102 have the same average data transfer rate. The data stream D101 is directed to the buffer memory BM201, from which the data stream is read out as synchronized by the timing signal CLK102. The state of fullness F201 of the buffer memory BM201 is measured/monitored. The state of fullness has been given the reference value Fref201. After this, the difference between the actual value and the reference value of the state of fullness is filtered by the low-pass filter LPF201. The momentary frequency of the timing signal CLK102 is controlled on the basis of the output of the low-pass filtering. Low-pass filtering LPF201 is used in order to prevent the frequency variation of the regenerated timing signal CLK102 from exceeding the limits permitted.
The problems entailed by the prior art solution presented above can be studied from FIG. 1. This method is not able to determine whether the reduction in the fullness of the buffer memory is caused by the fact that the frequency of the regenerated timing signal CLK102 is higher than the frequency of the timing signal CLK101, or that data transmission is momentarily prevented and/or the data transmission delay is momentarily higher than normal. Also, the system is not able to tell whether the frequency of the timing signal CLK102 is too low or whether the transmission delay is momentarily lower than normal. For this reason, various disturbances in the network significantly increase the risk that incorrect adjustment is performed on the frequency of the timing signal CLK102. This naturally increases the risk that the momentary frequency of the timing signal CLK102 differs considerably from the momentary frequency of the timing signal CLK101.
Another prior art method for regenerating the timing signal CLK102 is based on time stamps. In this method, time stamp information, which indicates the amount of time measured by the timing signal CLK101 between the transmission of consecutive time stamps, is added to the data stream D102 in the network element VE101. In the network element VE102, the difference between the arrival times of the time stamps is measured by means of the timing signal CLK102. By comparing the time difference indicated by the timing signal CLK101 and included in the time stamps with the time difference measured by the timing signal CLK102, a quantity indicating the frequency difference between those timing signals is obtained. The data communication network between the network elements VE101 and VE102 may cause a difference between the transmission delays of different time stamps. Therefore, an interference component with a zero average is generated in the quantity indicating the frequency difference, and low-pass filtering is applied in order to remove it. The momentary frequency of the timing signal CLK102 is adjusted on the basis of the output of the low-pass filtering. The problem caused by the fact that data being transferred is lost at times can be eliminated by marking consecutive time stamps in such a way that a possible loss of a time stamp is noticed. In this way, incorrect frequency adjustment measures caused by the loss of data being transferred can be avoided.
Let us assume that the time between the moments of reception of consecutive time stamps measured as the number of cycles of the timing signal CLK102 is higher than its reference value. This may be due to the fact that the frequency of the timing signal CLK102 is higher than the frequency of the timing signal CLK101 and the cycle length of the CLK102 signal is thus too small, or the fact that the data transmission delay is increasing. The problem with the second prior art method presented is the fact that the phenomena caused by the variation of the transmission delay look the same as the phenomena caused by the frequency difference. This causes the risk that incorrect frequency adjustment is carried out. Correspondingly, the system is not able to tell whether the frequency of the timing signal CLK102 is too low or whether the transmission delay is decreasing.